1. Field of the Invention
The present invention relates to a semiconductor memory device and more particularly to a circuit for controlling an input/output line (hereinafter, referred to as an "IO line") precharge in synchronization with a clock signal and a method for IO line precharge.
2. Description of Related Art
Semiconductor memory devices, particularly dynamic random access memories (DRAMs), are widely used in electronic systems for storing digital information. As the electronic systems operate at faster processing speeds, the access time for reading or writing data becomes a significant factor in the DRAM design. Hence, various techniques are used for improving DRAM access time. For example, "nibble mode" operation accesses a series of four sequential bits after accessing the first bit of the series. "Burst mode" operation sequentially accesses a full page or a row of bits after accessing the first bit of the page or the row. In the burst mode operation, after the input of an initial address of the first bit, subsequent addresses for the page or the row are internally generated without input of the subsequent addresses to the DRAM. Thus both the nibble and burst mode operations shorten DRAM access time by eliminating address re-loading delays associated with the subsequent bits.
Thc time from the input of a column address strobe (CASB) command to a data output is often called address access time t.sub.AA. To decrease the address access time t.sub.AA, the time required for precharging IO lines to a predetermined voltage, for example, a power supply voltage or half the power supply voltage, must be reduced because a column selection line (CSL) is enabled after IO lines are precharged. This is described below in detail.
FIG. 1 is a block diagram showing a known DRAM device 1 according to the prior art, which operates in synchronization with an externally applied clock signal (an external clock signal). The DRAM 1 has a memory cell array 10, and the memory cells in the array 10 are arranged at intersections of word lines WLi (i=0 to m) and bit lines BLj (j=0 to n). Each row of the memory array 10 is commonly referred to as a page. The bit lines BLj are divided into two groups, each of which includes pairs of the bit lines BLj. The first group includes bit line pairs BL0 and BL1, BL4 and BL5, . . . , BLn-3 and BLn-2, and the second group includes bit line pairs BL2 and BL3, BL6 and BL7, . . . , BLn-1 and BLn. A row decoder circuit 20 selects and drives one of the word lines WLi.
IO line pairs IOi and IOiB (i is 2 or more) are at the left side of the array 10, and IO line pairs IOj and IOjB (j is 2 or more) are at the right side of the array 10. FIG. 1 shows only a pair of the IO lines IOi and IOiB and a pair of the IO lines IOj and IOjB. The IO lines IOi and IOiB connect to an IO line driver circuit 30 (a first IO line driver), which in response to a signal CA8B drives the IO lines IOi and IOiB with data to be written. A precharge circuit 40 (a first precharge circuit), which is controlled by a precharge signal PIOP_8B from a precharge controller 120, precharges the IO lines IOi and IOiB. Similarly, the IO lines IOj and IOjB connect to an IO line driver circuit 30' (a second IO line driver), which drives the IO line pair IOj and IOjB with data to be written in response to a signal CA8 that is complementary to the signal CA8B. A precharge circuit 40' (a second precharge circuit), which is controlled by a precharge signal PIOP_8 from a precharge controller 120, precharges the IO lines IOj and IOjB.
The bit lines, for example, BL0 and BL1, as a pair, connect either to the IO lines IOi and IOiB or to the IO lines IOj and IOjB through bit line sense amplifiers 50 and column selection transistors ST. The gates of the column selection transistors ST connect to a column decoder circuit 80 through column selection lines CSL0 to CSLn. In operation, the IO lines IOi and IOiB are precharged, and the IO lines IOj and IOjB have data to be written/read to/from a memory cell associated with a selected word line and a selected bit lines. When the IO lines IOi and IOiB carry data for writing, the IO lines IOj and IOjB are precharged. An access to the array 10 is performed through the IO lines IOi and IOiB or the IO lines IOj and IOjB.
The above-described IO multiplexing and precharging techniques are disclosed in U.S. Pat. No. 4,754,433, entitled "DYNAMIC RAM HAVING MULTIPLEXED TWIN I/O LINE PAIRS", U.S. Pat. No. 5,761,146, entitled "DATA IN/OUT CHANNEL CONTROL CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE HAVING MULTI-BANK STRUCTURE", U.S. Pat. No. 5,742,185, entitled "DATA BUS DRIVE CIRCUIT FOR SEMICONDUCTOR MEMORY DEVICE", and U.S. Pat. No. 5,734,619, entitled "SEMICONDUCTOR MEMORY DEVICE HAVING CELL ARRAY DIVIDED INTO A PLURALITY OF CELL BLOCKS", which are incorporated herein by their entireties.
The precharge controller 120 includes a write interrupt read (WIR) detector 90, an address transition detector 100, and a precharge signal generator 110, and generates the precharge signals PIOP_8B and PIOP_8 when a write interrupt WI occurs. The write interrupt WI starts a write operation through one of the IO lines IOi and IOiB and the IO lines IOj and IOjB and then a write/read operation is performed through the other of the IO lines IOi and IOiB and the IO lines IOj and IOjB. A known circuit diagram of the WIR detector 90 is illustrated in FIG. 2. Thc WIR detector 90 includes two NOR gates G1 and G4, a transmission gate TG1, a latch L1 including two invertors INV2 and INV3, two NAND gates G2 and G3, an invertor INV4, and a pulse generator 91.
In FIG. 2, a signal PWR indicates an operation state at the previous clock cycle, wherein the high and low levels of the signal PWR respectively denote a write operation and a read operation. A signal PWRF indicates an operation state at the present clock cycle. When the signal PWRF is low, a read operation is performed during the present clock cycle. When the signal PWRF is high, a write operation is performed at the present clock cycle. The signal PWRF is not synchronized with the external clock signal. Namely, the signal PWRF is supplied directly into the WIR detector 90 through a buffer circuit (not shown) without setup or hold time. Signals PCF and PCSF, which are not synchronized with external clock signal and are supplied directly into the WIR detector 90 without setup and hold time, indicate a column address strobe signal CASB and a chip select signal CSB, respectively.
The operation of the WIR detector 90 is set forth below with reference to FIGS. 1 and 2. A write interrupt read operation occurs when a write operation is performed in association with the IO lines IOi and IOiB, and then a read operation is required in association with the IO lines IOj and IOjB. When the write interrupt read operation occurs, the signal PWRF becomes low. Since the signal PWR is high, an output signal A of the NOR gate G1 becomes low. When a clock signal PCLKF from a clock buffer 130 is high, an output signal B of the NAND gate G2 becomes low. This makes an output signal C of the NOR gate G4 transit from low to high, since both inputs of the NOR gate G4 are then low. Accordingly, the pulse generator 91 activates a write interrupt read detection signal PWIR to a high level.
On the other hand, when the write operation in association with the IO lines IOi and IOiB is interrupted, and then a write operation is required in association with the second IO lines IOj and IOjB, that is, when a write interrupt write (WIW) operation occurs, the signal PWRF remains high. Since the signal PWR is high, the output signal A of the NOR gate G1 is low. Successively, when a clock signal PCLKF from the clock buffer 130 is high, the output signal B of the NAND gate G2 remains high because an input signal of the NAND gate G2 from the inverter INV4 is low. Therefore, the input signal C and the output signal PWIR of the pulse generator 91 continue to be low.
The WIR detector 90 makes the signal PWIR activated high and inactivate low, respectively when the read operation after the write interrupt is required (that is, at the WIR operation), and when the write operation thereafter is required (that is, at the WIW operation).
FIG. 3 shows the address transition detector 100 that includes two pulse generators 101 and 102. Receiving a signal CA8 as its input signal, the pulse generator (a first pulse generator) 101 includes a delay circuit having three invertors INV11 to INV13, three resistors R7 to R9, and three MOS capacitors C6 to C8 connected to one another as illustrated in FIG. 3. The pulse generator 101 further includes a NAND gate G6 having three input terminals, which receive an output signal of the delay circuit, the signal CA8 and the signal PWR, respectively, and an output terminal outputting a first address transition detection signal PATD1. Similarly, receiving a complementary signal CA8B of the signal CA8 as its input signal, the pulse generator (a second pulse generator) 102 is implemented similarly to the first pulse generator 101, and description thereof is thus omitted. When the signal CA8 transits from low to high, the first address transition detection signal PATD1 becomes low for a time determined by the delay circuit, and a second address transition detection signal PATD2, which is from the second pulse generator 102, remains high. On the contrary, when the signal CA8B transits from low to high, the second address transition detection signal PATD2 becomes low for the delay time, and the first address transition detection signal PATD1 remains high.
The signals CA8 and CA8B of FIG. 3 are supplied from the address buffer circuit 60 of FIG. 1 in synchronization with a rising edge of the clock signal PCLK. The signals CA8 and CA8B select either the first IO lines IOi and IOiB or the second IO lines IOj and IOjB. For example, when the signal CA8B is high, an access operation is performed through the first IO lines IOi and IOiB, and when the signal CA8 is high the access operation is performed through the second IO lines IOj and IOjB.
Referring to FIG. 3, the precharge signal generator 110 receives the write interrupt read detection signal PWIR and the first and second address transition detection signals PATD1 and PATD2, and generates first and second precharge signals PIOP_8B and PIOP_8. The generator 110 has six invertors INV17 to INV22 and three NAND gates G8, G9 and G10 connected to one another as shown in FIG. 3.
Referring to FIGS. 1 and 3, when the WIR operation is required, the signal PWIR from the write interrupt read detector 90 is high. Accordingly, regardless of the first and second address transition detection signals PATD1 and PATD2, the NAND gates G9 and G10 activate the first and second precharge signals PIOP_8B and PIOP_8 to high. When the first precharge signal PIOP_8B is activated, the precharge circuit 40 precharges the IO lines IOi and IOiB. Similarly, when the second precharge signal PIOP_8 is activated, the precharge circuit 40' precharges the IO lines IOj and IOjB.
Referring to FIGS. 1 and 3, when the WIW operation is required, the PWIR signal becomes low as described above, so that input terminals of the NAND gates G9 and G10 connected commonly to the invertor INV22 becomes high if a signal CA11B is also high. Thus, logic levels of the first and second precharge signals PIOP_8B and PIOP_8 are determined according to those of the first and second address transition detection signals PATD1 and PATD2. Column addresses for the WIW operation are provided into the address buffer circuit 60 from the outside, and then the signals CA8 and CA8B from the address buffer circuit 60 are supplied to the address transition detector 100 in synchronization with a rising edge of the clock signal PCLK.
When the signals CA8 and CA8B are respectively high and low, the first address transition detection signal PATD1 from the first pulse generator 101 of the detector 100 pulses low, and the second address transition detection signal PATD2 from the second pulse generator 102 the detector 100 remains high. When the precharge signal generator 110 receives the first address transition detection signal PATD1 of the low level and the second address transition detection signal PATD2 of the high level, the first precharge signal PIOP_8B becomes high, and the second precharge signal PIOP_8 becomes low. As a result, only the IO lines IOi and IOiB are precharged by the first precharge circuit 40 which the first precharge signal PIOP_8B of the high level activates.
Accordingly, the precharge signal generator 110 keeps both the first and second precharge signals PIOP_8B and PIOP_8 high when the WIR operation is requested after the write interruption. The precharge signal generator 110 pulses one of the first and second precharge signals PIOP_8B and PIOP_8 high when the WIW operation is requested after the write interruption.
As described above, when an access operation through the IO lines IOj and IOjB is requested after a write operation through the IO lines IOi and IOiB, that is, when a write interrupt read/write (WIW/WIR) operation is requested, the IO lines IOi and IOiB have to be precharged before the access through the second IO lines IOj and IOjB. The reason for this is as follows. After data is written in a selected memory cell MC (FIG. 1) through the IO lines IOi and IOiB, the array 10 is accessed through the IO lines IOj and IOjB. If the access operation through the IO lines IOj and IOjB and the column selection line CSLn is performed without precharging the IO lines IOi and IOiB, the data written in the memory cell MC through the IO lines IOi and IOiB can be reversed. Accordingly, a write error could occur at the WIW/WIR operation. This is because the column selection transistors ST associated with the IO lines IOi and IOiB, and IOj and IOjB are commonly coupled with the column selection line CSLn. Therefore, IO lines having written data before a write interrupt must be precharged through a corresponding precharge circuit.
Referring to FIGS. 1, 3, and 4A, a conventional write interrupt read operation is as follows. Assuming that a write operation is performed through the IO lines IOi and IOiB at a clock cycle, for example, n-th clock cycle as shown in FIG. 4A. When the WIR operation is required for the IO lines IOj and IOjB at a next clock cycle, for example, (n+1)th clock cycle, a write enable signal WEB is high, and the column address strobe signal CASB is toggled. Accordingly, at the (n+1)th clock cycle, the WIR detector 90 responds to the signal PWRF of a low level and generates the signal PWIR of a high level in synchronization with a rising edge of the clock signal PCLKF as described with reference to FIG. 2. The clock signal PCLKF slightly leads the clock signal PCLK. Continuously, the precharge signal generator 110 (FIG. 1) makes the first and second precharge signals PIOP_8B and PIOP_8 high. As a result, the IO lines IOi and IOiB, and IOj and IOjB are precharged through corresponding precharge circuits 40 and 40', which are activated in response to the first and second precharge signals PIOP_8B and PIOP_8, respectively. After the IO precharge operation has been ended, a column selection line CSL associated with the WIR operation is selected through the column decoder circuit 80, and data read from the array 10 is loaded onto the IO lines IOj and IOjB.
Referring to FIGS. 1, 3, and 4B, a conventional write interrupt write operation in a normal mode is as follows. A write operation is performed through the IO lines IOi and IOiB at n-th clock cycle as shown in FIG. 4B. When the WIW operation is required for the IO lines IOj and IOjB at next clock cycle, the write enable signal WEB and the column address strobe signal CASB are toggled. Then, the write interrupt read detection signal PWIR of the WIR detector 90 continues to be low, so that the input terminals of the NAND gates G9 and G10 connected to the inverter INV22 have the logical high level. Therefore, the first and second address transition detection signals PATD1 and PATD2 determine the logic states of the first and second precharge signals PIOP_8B and PIOP_8.
Further, an address signal A8 from among the column address signals, which are provided from the outside for the WIW operation, is latched in a latch (not shown) of the address buffer circuit 60 in synchronization with a falling edge of the clock signal PCLK at thc n-th clock cycle. Then, the address signal A8 held in the latch is converted and outputted into address signals CA8 and CA8B in synchronization with a rising edge of the clock signal PCLK at the (n+1)th clock cycle. Assuming that the address signal A8 is high, the address signal CA8 becomes high, and the complementary address signal CA8B becomes low. As a result, the first pulse generator 101 of the address transition detector 100 pulses the signal PATD1 to the low level in response to the signal CA8. At this time, the second address transition detection signal PATD2 remains high. The precharge signal generator 110 produces the first precharge signal PIOP_8B of a high level and the second precharge signal PIOP_8 of a low level, so that only the IO lines IOi and IOiB are precharged. After the precharge operation has been completed, a column selection line CSL associated with the WIW operation is selected through the column decoder circuit 80, and then data loaded onto the IO lines IOj and IOjB is written to the array 10.
Referring to FIGS. 1, 3, and 4C, a conventional write interrupt write operation in a full page mode is as follows. At the full page mode, for example, a half of the memory cells connected to a selected word line (page) are accessed through the IO lines IOi and IOiB, and then the other half of the memory cells are accessed through the second IO lines IOj and IOjB. As described above, in order to prevent a write error, the IO lines IOi and IOiB have to be precharged prior to the access through the IO lines IOj and IOjB. The WIW operation at the full page mode is the same as the WIW operation at the normal mode of FIG. 4B except that an address signal PCA8B instead of the address signal A8 is provided from a burst counter 70.
In the above-described IO precharge scheme, the WI operation is divided into the WIR and WIW operations. The WIW operation at a normal or full page mode precharges the first or second IO lines by use of address transition information, that is, the address transition detection signals PATD1 and PATD2. The WIR operation of the normal mode precharges the first and second IO lines by use of an external command transition information, that is, the write interrupt read detection signal PWIR. According to the IO precharge scheme, as shown in FIG. 4B, the IO precharge time of the normal mode WIW operation is delayed by the time .DELTA.t relative to that of the normal mode WIR operation. Thus, a column selection line CSL is enabled after the time At at the WIW operation. This also happens in the full page mode WIW operation. The delay occurs because a command transition detection time occurs prior to an address transition detection time. That is, the WIR and WIW operations are performed in synchronization with rising edges of the clock signal PCLKF and of the clock signal PCLK, respectively, and the clock signal PCLK occurs later than the signal PCLKF. Furthermore, a transmission path of the address signal supplied to the address transition detector 100 is longer than that of a command signal supplied into the WIR detector 90.
Accordingly, a write time at the WIW operation is longer than that at the WIR operation. This affects the time t.sub.AA from the CASB command input to the data output, so that the address access time t.sub.AA becomes longer. Therefore, the address access and write time of the prior DRAM device 1 are extended.